The Complete Implementation Path from Chip to System (Part 1)
HART Technology Solutions White Paper
The Complete Implementation Path from Chip to System (Part 1)
Summary
In the field of industrial automation, HART (Highway Addressable Remote Transducer) protocol serves as a core technological link connecting traditional analog equipment with modern digital management systems. Having undergone nearly forty years of industrial field validation, HART has become one of the most widely deployed field device communication protocols globally. By using Bell 202 FSK modulation technology, digital communication signals are superimposed on a traditional 4-20mA analog current loop, achieving dual-mode coexistence of " analog transmission + digital communication . " This design allows companies to endow existing equipment with digital capabilities such as remote configuration, real-time diagnostics, and multivariate transmission without interrupting existing control loops or re-laying cables.
This document aims to provide system engineers, hardware developers, and project decision-makers in the field of industrial automation with a full-stack technology guide covering chip selection, hardware design, protocol stack development, and system integration. It also delves into domestic substitution paths and future evolution trends, helping local enterprises build independent and controllable HART technology capabilities .
I. In-depth Analysis of the HART Protocol Technical Architecture
The HART protocol follows the specifications of the physical layer, data link layer, and application layer in the OSI seven-layer model. The ingenuity of its technical architecture lies in the high degree of coordination between the layers and its deep adaptation to the harsh environments of industrial sites. Understanding its layering mechanism is the theoretical foundation for designing reliable HART systems.
1.1 Physical Layer: FSK Modulation and Signal Coexistence Mechanism
The HART physical layer employs Bell 202 standard Frequency Shift Keying (FSK) modulation technology, with 1200 Hz representing logic “1” and 2200 Hz representing logic “0”, and a constant baud rate of 1200 bps. The digital communication signal is superimposed on a 4-20 mA analog current loop with a weak current fluctuation of ±0.5 mA peak-to-peak. Since the time average of the FSK signal is zero, it has no substantial impact on the transmission accuracy of the analog signal.
Table 1: Core Technical Parameters of HART Physical Layer
| Modulation method | Bell 202 FSK (Frequency Shift Keying) |
| Carrier Frequency | Logic “1”: 1200 Hz | Logic “0”: 2200 Hz |
| Baud Rate | 1200 bps (fixed) |
| Signal Amplitude | ±0.5 mA (peak-to-peak value, superimposed on the 4-20 mA loop) |
| Load Resistor | 250 Ω (standard, produces a 1-5 V voltage drop for easy measurement) |
| Transmission Distance | Theoretically, the maximum length is 3,000 m (depending on cable specifications and topology). |
The FSK modulated signal is injected into the current loop through a capacitive coupling network. The coupling circuit design must ensure low impedance paths at 1200 Hz and 2200 Hz, while exhibiting high isolation characteristics in the DC and low-frequency bands to avoid interference with the analog signal. This “frequency division multiplexing” mechanism is the fundamental guarantee for the seamless coexistence of the HART protocol with 4-20 mA analog systems.
1.2 Data Link Layer: Master-Slave Architecture and Communication Protocol
The HART data link layer adopts a strict “1 Master / n Slaves” communication architecture, supporting two networking modes:
Point-to-Point Mode: The master device communicates with a single slave device. A 4-20 mA analog signal is used for process variable transmission, while the digital channel carries device configuration and diagnostic information. Suitable for upgrading traditional control loops.
Multi-drop mode: Up to 15 slave devices can be connected to a single bus (modern HART-IP expands to more nodes), using only digital channels for communication, with a fixed analog current of 4 mA for device power supply. Suitable for distributed sensor networks.
The data link layer frame format follows strict structured specifications, including a preamble, delimiter, address field, command field, data field, and check sequence to ensure transmission reliability in noisy industrial environments. The HART protocol supports both long frame and short frame formats. The former supports a 38-bit unique device identifier, while the latter is used to simplify addressing and broadcast communication.
1.3 HART Protocol Stack Layered Architecture
A complete HART protocol stack consists of multiple core layers, each with clearly defined responsibilities and interfaces, providing standardized assurance for device interoperability:
Table 2: HART Protocol Stack Layered Architecture and Function Mapping
| Physical Layer | FSK modulation and demodulation, signal coupling, current loop drive, and loop power supply management. |
| Data Link Layer | Frame encapsulation/parsing, CRC check, master-slave scheduling, collision detection and retransmission |
| Application Layer | Universal Commands, Common Practice Commands, and Device-Specific Commands |
| Transport Layer | The segmented transmission mechanism introduced in HART 7 supports reliable transmission of large data packets. |
II. Core Chip Selection and Key Component Matching
The core of HART system hardware design lies in the coordinated selection of the HART chip, DAC, and MCU . The HART chip directly determines the compliance and reliability of HART communication, the DAC determines the accuracy and stability of the analog output, and the MCU carries the protocol stack operation and application logic processing. This chapter provides mass-produced and verified selection solutions based on engineering practice.
2.1 HART Chip Comparison and Selection
The HART communication chip is the core component of the system, responsible for the modulation and demodulation of FSK signals. The table below compares current mainstream communication chip solutions, covering three main categories: high-end imported chips, classic imported chips, and domestic alternatives:
Table 3: HART Communication Chip Comprehensive Comparison and Selection Table
| Model | Manufacturer/Positioning | Temperature range | Core Features | Applicable Scenarios |
AD5700 AD5700-1 | ADI imported high-end | -40°C ~ +125°C | Ultra-low power consumption (<2 μA sleep), built-in ADC Oscar circuit, configurable interface level | High-precision transmitters, high-end industrial instruments, and applications in harsh environments |
A5191 A5191HRT | Imported classic model | -40°C ~ +85°C | Industrial-grade wide temperature range, mature peripheral circuitry, abundant documentation, and a complete ecosystem. | Upgrading existing equipment, migrating legacy solutions, and using general-purpose HART modules. |
| HT5700 | Microcyber Domestic compatibility | -40°C ~ +125°C | Pin-to-Pin compatible with AD5700, cost reduction of 30%-50%, localized technical support. | Domestic substitution projects, cost-sensitive mass applications, and the need for independent control. |
| HT1200M | Microcyber Domestic Simplified | -40°C ~ +85°C | Monolithic integrated design, minimal peripheral components (reduced by 60%+), stable and reliable, small package | Low-cost HART module, easy slave device, space-constrained applications |
Selection Recommendation: For domestic substitution and cost-sensitive batch projects, Microcyber HT5700 (Pin-to-Pin compatible with AD5700) and HT1200M (extremely simple peripheral design) provide highly competitive alternatives. Actual test results show that their communication performance is at the same level, while the cost can be reduced by more than 50% .
2.2 Preferred Scheme for Auxiliary Devices
Besides the communication chip, the selection of DAC and MCU also affects the overall system performance. The following are recommended auxiliary components that have been proven in mass production:
Table 4: Optimal DAC Chip Scheme
| DAC model | Manufacturers | Core Features | Applicable Scenarios |
| AD5420 | ADI | 16-bit precision, HART signal injection port, 4-20 mA output | HART transmitters are the preferred choice for high-precision applications. |
| AD5421 | ADI | 16-bit precision, HART compatible, loop-powered | Loop-powered field instruments |
| DAC8830 | TI | 16-bit ultra-low power consumption, single power supply | Battery-powered wireless HART devices |
Table 5: MCU Preferred Scheme
| MCU Model | Core | Core Features | Applicable Scenarios |
| STM32L0/L4 | ARM Cortex-M0+/M4 | Ultra-low power consumption, abundant peripherals, and a mature ecosystem | General-purpose HART devices, batch projects |
| ADuCM360 | ARM Cortex-M3 | 24-bit ADC integration, industrial-grade precision, ADI ecosystem | High-precision industrial transmitters and process control instruments |
The above is the core content of this issue of the “HART Technology Solution White Paper”. We have systematically broken down the underlying logic and key technical points of HART communication, from the origin of the protocol and the physical layer principle to the chip-level implementation.
Next, we will delve into hardware architecture and embedded protocol stack implementation, detailing the engineering path of HART from circuit design and signal conditioning to protocol stack porting, truly applying the technical principles to mass-producible hardware solutions.
